1. Field of the Invention
The present invention relates to a pulse generator for use in an integrated circuit arrangement.
2. Description of the Prior Art
As shown in FIG. 1, a conventional pulse generator comprises a delay circuit unit 11 having three inverters 10 connected in series and a comparator unit consisting of a NAND gate unit 12 with dual input terminals, wherein the output terminal 11a of the delay unit 11 is connected to one input terminal 12a of the dual input NAND unit 12, and the input terminal 11b of the delay unit 11 is coupled with the other input terminal 12b of the dual input NAND unit 12. The coupled common terminal of both said input terminals 11b and 12b is used as a signal input terminal 13 of the pulse generator and an output terminal 12c of the dual input NAND unit 12 is used as a signal output terminal 14 of the pulse generator.
In the conventional pulse generator as described above, if a pulse signal P1 with a sufficiently long pulse duration is entered as an input signal for the pulse generator, a pulse signal P2 is generated from the signal output terminal 14 of the pulse generator with a constant pulse duration rising up at the time of the rising edge of the pulse signal P1. At this time, the pulse duration of the output pulse signal P2 is equal to the delay time t.sub.3 of the delay unit 11.
Therefore, if it is necessary to generate an output pulse signal with a long pulse duration, the delay unit is constituted with an odd number of inverters connected in series according to the necessity of the pulse duration. Moreover, in FIG. 2, the signal P3 is an output pulse signal of the delay unit 11 which is applied to the other input terminal 12a of the dual input NAND gate 12.
However, as shown by dotted lines in FIG. 2, there has been a problem in the conventional pulse generator mentioned above that, when the pulse duration of the input pulse signal P1 is shorter than the delay time t.sub.3 of the delay unit 11, the pulse duration of the output pulse signal P2 becomes equal or shorter than that of the input pulse signal P1, and furthermore it occasionally occurs that an output pulse signal can not be obtained in a specific delay unit 11 with a specific delay characteristic.